Micron delivered some fairly large information at the moment, saying it has begun quantity manufacturing of the trade’s first 232-layer triple-level cell (TLC) NAND flash reminiscence chips with big beneficial properties in space density, capability, vitality effectivity, and efficiency. In quick, it is an enchancment over 176-layer NAND in virtually each conceivable method.
Or to place it in Micron’s personal phrases, it is a “watershed moment for storage innovation,” serving as the primary proof that it will probably scale 3D NAND flash to greater than 200 layers in quantity manufacturing. Not that it was a simple achievement by any stretch, however an essential one.
“This groundbreaking technology required extensive innovation, including advanced process capabilities to create high aspect ratio structures, novel materials advancements and leading-edge design enhancements that build on our market-leading 176-layer NAND technology,” stated Scott DeBoer, government vice chairman of expertise and merchandise at Micron.
Today’s packaging applied sciences are more and more reliant on stacking options. Micron likens this to constructing in an costly, overcrowded metropolis. Instead of increasing outward, which isn’t a viable or price efficient strategy to improve density, taller buildings benefit from vertical house so as to add extra ranges and items in the identical compact footprint.
It’s an oversimplified analogy, however Micron’s 3D NAND takes the identical basic strategy. According to Micron, its 232-layer answer permits the trade quickest NAND I/O pace at 2.4GB/s, which is 50 p.c sooner than the earlier technology 176-layer answer. It additionally delivers as much as One hundred pc greater write bandwidth and greater than 75 p.c greater learn bandwidth per die, the corporate claims.

“In addition, 232-layer NAND introduces the world’s first six-plane TLC production NAND.3 It has the most planes per die of any TLC flash3 and features independent read capability in each plane,” Micron provides.
According to Micron, using a six-plane structure means fewer collisions between write and browse instructions, which in flip delivers important system-level quality-of-service (QoS) enhancements.
There are additionally advantages on capability facet of the equation. Leveraging a 232-layer design has allowed Micron for the primary time to realize a 1-terabit (Tb) TLC die, which is double that of its 176-layer design. It’s touting the best TLC density per sq. millimeter (14.6 Gb/mm2) ever made, with an space density that’s wherever from 35-One hundred pc higher than competing TLC merchandise presently obtainable.
What this all means is that drive makers will be capable of ship sooner and extra capacious SSDs, and simply in time for a push into PCIe 5.0 territory. It feels like Micron will give its personal Crucial model first dibs, however says to count on extra product and availability bulletins.