Intel’s LEGO-Like Chiplet Design For Next-Gen Meteor Lake, Arrow Lake & Lunar Lake “3D Foveros” CPUs Detailed
On: August 23, 2022
Yesterday, we reported just a few key particulars of Intel’s next-gen CPUs which characteristic a really LEGO-Esque design due to the 3D Foveros packaging know-how. The new CPUs that might be placing the tech to good use embody Meteor Lake, Arrow Lake, and Lunar Lake. Today, at Hot Chips 34, Intel is giving us a extra detailed take a look at what goes into growing the Meteor Lake CPUs and past.
Intel 3D Foveros Packaging Tech Brings LEGO-Like Design To Next-Gen Meteor Lake, Arrow Lake & Lunar Lake CPUs
The key enabler of Intel’s next-gen CPUs is Foveros, a complicated inter-die chiplet packaging tech. Foveros will are available three flavors, beginning first with the usual design that might be used for high-yield and high-volume manufacturing, moving on to Foveros Omni that mixes and matches tiles within the base die advanced, providing as much as 4x interconnect bump density vs EMIB and lastly, Foveros Direct which provides 16x interconnect density versus the unique Foveros whereas delivering decrease latency, greater bandwidth and lowered energy/die necessities. Following are the bottom specs for the trio of Foveros options:
Beyond Alder Lake and Raptor Lake CPUs that are the primary designs to characteristic a hybrid core format, Intel is planning to make the most of its 3D Foveros packaging to usher in its personal multi-chiplet period. Chipzilla has deliberate on releasing three merchandise that may leverage this know-how. The next-generation processors embody the 14th Gen Meteor Lake, fifteenth Gen Arrow Lake, and sixteenth Gen Lunar Lake households. Some of the principle highlights of those CPUs can be:
Intel Next Generation 3D Client Platform
Disaggregated 3D Client structure with CPU, GPU, SOC, and IO Tiles
Base tiles for Meteor Lake and Arrow Lake to interconnect tiles with Foveros
Open “Chiplet” ecosystem via common chiplet interconnect categorical (UCIe)
2 of 9
Starting first with Intel Meteor Lake, the corporate confirmed off a model new chip format which provides us a greater take a look at the assorted tiles or chiplets (as you prefer to confer with them) with numerous IPs. The quad-tile format contains the CPU Tile, Graphics Tile, SOC Tile, and IOE Tile.
Intel did disclose the particular nodes these tiles can be primarily based upon. The major CPU tile might be utilizing the “Intel 4” or 7nm EUV course of node whereas the SOC Tile and IOE Tiles might be fabricated on TSMC’s 6nm course of node (N6). Intel calls Meteor Lake step one into the chiplet ecosystem within the shopper phase. According to trade sources, this is not the case and the tGPU for the Meteor Lake CPUs has all the time been a TSMC 5nm (N5) design.
So beginning with the dissection of every tile, first up, we’ve got the Compute Tile which is totally scalable throughout numerous core counts, core generations, nodes, and cache. Intel can combine and match not simply completely different core architectures inside its Foveros 3D bundle CPUs corresponding to Meteor Lake however they will additionally scale up or all the way down to a distinct node.
The similar is true for the graphics tile which may be scaled by way of core depend, node and cache too. These diagrams are only for illustration functions however they show a tGPU block scaling from 4 Xe cores (64 EUs) as much as 12 Xe Cores (192 EUs).
2 of 9
The SOC Tile may also be scaled up or down relying on the SKU. The major blocks listed below are the Low-Power IP (referring to the VPU), SRAM, IO, and a scalable voltage design. The similar is true for the final Tile, the I/O Extender, or IOE briefly. The tile is totally scalable by way of the variety of lanes, bandwidth, protocols, and pace.
With the tiles out of the best way, it is time to put collectively all the things and for that, Intel has proven a breakdown of how the CPU dies are organized collectively. The prime layer has a back-side metallization and can also be where the Foveros passive die sits. Right beneath these is the recognized good tiles that we have simply mentioned above. These tiles are related to the Base Tile utilizing a 36um pitch (die-to-die) inter-connect. The Base Tile comes with massive capacitance and has steel layers for IO/energy supply and D2D routing.
2 of 9
Intel additionally gives a close-up of the Base Tile’s steel layer which options 3D capacitors and die-to-die energy supply plus bundle I/O routing. Each steel layer is modular with lively silicon for logic and reminiscence. The prime and backside have bundle bumps for interconnecting with the highest & backside layers.
The configuration proven right here can also be a mobile-specific chip with a 6+4 (6 P-Cores + 4 E-Cores) format. You may notice that there are two D2D (Die-To-Die) hyperlinks between the CPU/IOE Tile and the Graphics Tile main into the SOC Tile. This is a part of the Foveros 3D Packaging and the blue crew states that there is a passive interposer on prime of the principle chiplets which relies on a 22nm (FFL) course of from Intel itself. This interposer at present serves no goal however the firm plans to make use of lively chiplets inside it sooner or later with extra superior packaging applied sciences. The Intel Meteor Lake CPUs do not make the most of EMIB know-how.
The FDI (Foveros Die Interconnect) know-how provides:
A Low Voltage CMOS Interface
High Bandwidth, Low Latency
Synchronous & Asynchronous Signaling
Low Area Overhead
Operation @ 2GHz, 0.15-0.3 pJ/bit
The Interconnects between the CPU and the SOC have a mainband width of round 2K (2x IDI), the Graphics and SOC tiles have a interconnect mainband width of round 2K too (2x iCXL) whereas the SOC and IOE tiles have a mainband width round 1K (IOSF, 4x Display Port).
Another key space where Intel’s Meteor Lake CPUs have improved quite a bit is the utmost turbo energy functionality. Since its inception and with the assistance of co-optimizations, the Meteor Lake chips can obtain greater turbo energy capabilities than the earlier technology Alder Lake CPUs whereas using the model new “Intel 4” course of node. The complete capacitance has additionally touched 500 for the Meteor Lake Base Tile.
Intel offers us an old-school comparability between a Haswell and Meteor Lake CPU so far as their I/O capabilities are involved.
Another side that was touched upon by Intel is pricing. With prices of next-gen wafer costs going up with each new node, the price of growing a monolithic die can also be going to go up.
If you had been to take Meteor Lake as it’s and design it monolithically on a number one course of node, I’d say it truly is extraordinarily aggressive with that if not truly cheaper.
through Intel
Intel reveals {that a} disaggregated design like Meteor Lake with Tiled-architecture can ship greater efficiency, greater transistor efficiency uplifts, & higher IP refresh tempo throughout numerous course of nodes, all at greater energy effectivity versus a monolithic resolution.
2 of 9
Intel revealed that its Meteor Lake CPUs will scale from <10W to over 100W SKUs, providing CPU efficiency of a monolithic design in a disaggregated bundle. Furthermore, Intel clarified that 14th Gen Meteor Lake & fifteenth Gen Arrow Lake CPUs are certainly heading to each Desktop and Mobile platforms.
The Intel Meteor Lake CPUs are aiming for the 2023 launch window whereas Arrow Lake will begin delivery in 2024 as initially deliberate. Details on the next-generation LGA 1851 socketed platform for Meteor Lake & Arrow Lake CPUs may be discovered right here.
Intel Meteor Lake-P (6+8) CPU Chip Layout:
As far as sixteenth Gen Lunar Lake CPUs are involved, the household is claimed to be initially aimed on the 15W low-power cellular CPU phase nevertheless these unique plans can all the time change because the product remains to be just a few years away from launch.
2 of 9
Furthermore, it will not be the primary time Intel sticks with a mobile-only or partial-desktop launch for a CPU household. We have already seen them do that with Broadwell and extra lately with the Ice Lake and Tiger Lake CPU households.
