A latest report from Chips and Cheese reveals that Intel has contained the proportional improve in latency of the L2 caches within the next-gen Raptor Lake-S (thirteenth Gen Core CPUs).

Intel thirteenth Gen Raptor Lake Optimizes twelfth Gen Alder Lake Latencies Across A Wider Array of Cores

The upcoming Intel thirteenth Gen Raptor Lake CPUs will improve the L2 cache sizes in comparison with the Alder Lake collection. The present era of Alder Lake-S processors is powered with the 1.25 MB Golden Cove P-cores, whereas the brand new Raptor Cove P-Cores, totaling eight every, have 2 MBs of L2 cache devoted to every core.

The quantity equals a sixty p.c improve within the upcoming era in comparison with the present Alder Lake cores. Additionally, the Gracemont E-core clusters equal to 4 E-cores are two instances the scale of the L2 cache shared all through the 4 cores within the cluster, which is now elevated to 4 MB. L3 cache between the P and E-core additionally see a rise to 36 MB from the earlier 30 MB.

Chips and Cheese adopted and calculated the latencies in L2 cache latencies of earlier Intel microarchitectures and found a rise in latency ranges. Increased caches drive efficiency since extra knowledge is open and close to the processor’s cores, limiting the extra appreciable fetch/retailer process that travels to the RAM. Luckily, energy, warmth, die-area, transistor depend, and latency are comparatively faster than a system’s DRAM.



2 of 9

Furthermore, OneRaichi has identified that the adjustments inside the cache construction of the Intel Raptor Lake thirteenth Gen CPUs have allowed for an enormous optimization in latencies general. The beforehand encountered wall between the P-Core and E-Core has now kind of disappeared which was as a result of inefficient latencies for the E-cores.

This is why I simply say the RPL is simply not solely a refresh.

you possibly can see the ringbus construction has some adjustments and it makes the boundary of the P and E core is nearly disappeared.

I suppose the community topology of ringbus is completely different.

— Raichu (@OneRaichu) August 23, 2022



2 of 9

Chips and Cheese report that the four-way associative 256 KB reserved L2 cache with the Skylake processor cores has an L2 cache latency equal to 12 cycles. Sunny Cove and Cypress Cove cores have a latency of 13 cycles as a result of 512 KB measurement improve. Willow Cove makes use of an associative cache (20-way), whereas Golden Cove makes use of solely ten. Furthermore, the latency will increase to 14 cycles. With Raptor Cove P-core on the horizon, the brand new core presents 2 MB of 16-way L2 cache and decreased latency of fifteen cycles.

This new report exhibits that intel has accomplished a major quantity of designing and testing to help with cache and energy administration to make the brand new cache extra power-friendly. Readers also needs to notice that the brand new thirteenth Gen Core Raptor Lake processors are constructed using the ten nm Enhanced SuperFin node at present used within the present era of Intel processors.

News Sources: TechPowerUP, Chips and Cheese, Raichu